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| HM628127HB Series 131072-word x 8-bit High Speed CMOS Static RAM ADE-203-350C (Z) Rev. 3.0 Nov. 19, 1996 Description The HM628127HB is an asyncronous high speed static RAM organized as 128-k word x 8-bit. It realize high speed access time (15/20 ns) with employing 0.8 m shrink CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM628127HB is packaged in 400-mil 32-pin SOJ for high density surface mounting. Features * Single 5 V supply * Access time 15/20 ns (max) * Completely static memory No clock or timing strobe required * Equal access and cycle times * Directly TTL compatible All inputs and outputs * 400-mil 32-pin SOJ package * Center VCC and VSS type pinout Ordering Information Type No. HM628127HBJP-15 HM628127HBJP-20 HM628127HBLJP-15 HM628127HBLJP-20 Access time 15 ns 20 ns 15 ns 20 ns Package 400-mil 32-pin plastic SOJ (CP-32DB) HM628127HB Series Pin Arrangement HM628127HBJP/HBLJP Series A3 A2 A1 A0 CS I/O1 I/O2 VCC VSS I/O3 I/O4 WE A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A4 A5 A6 A7 OE I/O8 I/O7 VSS VCC I/O6 I/O5 A8 A9 A10 A11 A12 (Top view) Pin Description Pin Name A0 to A16 I/O1 to I/O8 CS OE WE VCC VSS Function Address input Data input/output Chip select Output enable Write enable Power supply Ground 2 HM628127HB Series Block Diagram (LSB) A3 A2 A1 A0 A7 A6 A5 A4 (MSB) VCC Row decoder Memory matrix 256 rows x 512 columns x 8 bit (1,048,576 bits) VSS CS I/O1 . . . I/O8 WE CS Column I/O Input data control Column decoder CS (LSB) A13 A12 A11 A14 A15 A16 A10 A9 A8 (MSB) OE CS Function Table CS H L L L L Note: OE x H L H L x: H or L WE x H H L L Mode Standby Output disable Read Write Write VCC current I SB , I SB1 I CC I CC I CC I CC I/O High-Z High-Z Dout Din Din Ref. cycle -- -- Read cycle (1) to (3) Write cycle (1) Write cycle (2) 3 HM628127HB Series Absolute Maximum Ratings Parameter Supply voltage relative to VSS Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +7.0 -0.5* to V CC+0.5 1.0* /1.5* 0 to +70 -55 to +125 -10 to +85 2 3 1 Unit V V W C C C Notes: 1. VT min = -2.5 V for pulse width (under shoot) 10 ns 2. At still air condition 3. At air flow 1.0 m/s Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VCC* VSS * Input voltage VIH VIL 2 3 Min 4.5 0 2.2 -0.5* 1 Typ 5.0 0 -- -- Max 5.5 0 VCC + 0.5 0.8 Unit V V V V Notes: 1. VIL min = -2.0 V for pulse width (under shoot) 10 ns 2. The supply voltage with all VCC pins must be on the same level. 3. The supply voltage with all VSS pins must be on the same level. 4 HM628127HB Series DC Characteristics (Ta = 0 to +70C, VCC = 5V 10%, VSS = 0V) Parameter Input leakage current Output leakage current Operation power supply current Symbol Min IILII IILO I 15 ns cycle I CC 20 ns cycle I CC Standby power supply current 15 ns cycle I SB 20 ns cycle I SB I SB1 -- -- -- -- -- -- -- Typ*1 -- -- 120 100 55 45 -- Max 2 2 180 150 100 80 2 mA VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V mA CS = VIH, Other inputs = VIH/V IL Unit A A mA Test conditions Vin = VSS to V CC Vin = VSS to V CC CS = VIL, lout = 0 mA Other inputs = VIH/V IL --* 2 Output voltage VOL VOH -- 2.4 --* 2 -- -- 0.2*2 0.4 -- V V I OL = 8 mA I OH = -4 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. This characteristics is guaranteed only for L-version. Capacitance (Ta = 25C, f = 1.0 MHz) Parameter Input capacitance* 1 1 Symbol Cin CI/O Min -- -- Typ -- -- Max 6 8 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Input/output capacitance* Note: 1. This parameter is sampled and not 100% tested. 5 HM628127HB Series AC Characteristics (Ta = 0 to +70C, VCC = 5V 10%, unless otherwise noted.) Test Conditions * * * * Input pulse levels: 0 V to 3.0 V Input rise and fall time: 3 ns Input and output timing reference levels: 1.5V Output load: See figures (Including scope and jig) 5V 5V 480 Dout 255 30 pF Dout 255 480 5 pF Output load (A) Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW) Read Cycle HM628127HB-15 Parameter Read cycle time Address access time Chip select access time Output enable to outpput valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Chip selection to power up time Chip selection to power down time Symbol Min t RC t AA t ACS t OE t OH t CLZ t OLZ t CHZ t OHZ t PU t PD 15 -- -- -- 5 3 1 -- -- 0 -- Max -- 15 15 8 -- -- -- 7 7 -- 15 HM628127HB-20 Min 20 -- -- -- 5 3 1 -- -- 0 -- Max -- 20 20 10 -- -- -- 7 7 -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 Notes 6 HM628127HB Series Write Cycle HM628127HB-15 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Write disable to output in low-Z Output disable to output in high-Z Write enable to output in high-Z Note: Symbol Min t WC t AW t CW t WP t AS t WR t DW t DH t OW t OHZ t WHZ 15 12 10 10 0 0 8 0 3 -- -- Max -- -- -- -- -- -- -- -- -- 7 7 HM628127HB-20 Min 20 15 12 12 0 0 10 0 3 -- -- Max -- -- -- -- -- -- -- -- -- 7 7 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 1 9 8 6 7 Notes 1. Transition is measured 200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested. 2. Address should be valid prior to or coincident with CS transition low. 3. WE and/or CS must be high during address transition time. 4. if CS and OE are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them. 5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 6. t AS is measured from the latest address transition to the later of CS or WE going low. 7. t WR is measured from the earlier of CS or WE going high to the first address transition. 8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low. A write ends at the earliest transition among CS going high and WE going high. tWP is measured from the beginnig of write to the end of write. 9. t CW is measured from the later of CS going low to the the end of write. 7 HM628127HB Series Timing Waveforms Read Timing Waveform (1) (WE = VIH) t RC Address Valid address t AA t ACS t OH t CHZ CS t OE OE t OLZ t CLZ Dout High Impedance Valid data t OHZ Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL ) t RC Address t OH Dout Valid address t AA t OH Valid data 8 HM628127HB Series Read Timing Waveform (3) (WE = VIH, CS = VIL , OE = VIL )*2 tRC CS tACS tCLZ Dout ICC VCC supply current tCHZ High Impedance tPD High Impedance tPU 50% Valid data ISB 50% Write Timing Waveform (1) (WE Controlled) t WC Address Valid address t AW OE t CW CS*3 t AS WE*3 t OHZ Dout High impedance*5 t DW Din *4 t DH *4 t WP t WR Valid data 9 HM628127HB Series Write Timing Waveform (2) (CS Controlled) t WC Address Valid address t CW CS *3 t AW t WP WE *3 t AS t WHZ Dout t OW High impedance*5 t DW Din *4 t DH *4 t WR Valid data 10 HM628127HB Series Low VCC Data Retention Characteristics (Ta = 0 to 70C) This characteristics is guaranteed only for L-version. Parameter VCC for data retention Symbol VDR Min 2.0 Typ*1 -- Max -- Unit V Test conditions VCC CS VCC - 0.2 V (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V VCC = 3 V, VCC CS VCC - 0.2 V (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V See retention waveform Data retention current I CCDR -- 2 80 A Chip deselect to data retention time Operation recovery time Note: t CDR tR 0 5 -- -- -- -- ns ms 1. Typical values are at VCC = 3.0 V, Ta = 25C, and not guaranteed. Low V CC Data Retention Timing Waveform t CDR V CC 4.5 V Data retention mode tR 2.2 V V DR CS 0V VCC CS VCC - 0.2 V 11 HM628127HB Series Package Dimensions HM628127HBJP/HBLJP Series (CP-32DB) Unit: mm 32 20.71 21.08 Max 17 10.16 0.13 11.18 0.13 1 3.50 0.26 1.30 Max 0.80 +0.25 -0.17 0.43 0.10 0.41 0.08 1.27 9.40 0.25 0.10 Hitachi Code JEDEC Code EIAJ Code Weight 12 2.85 0.12 CP-32DB MO-061-AB SC-638 1.2 g 0.74 16 HM628127HB Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 13 HM628127HB Series Revision Record Rev. 0.0 1.0 2.0 Date Sep. 9, 1995 Nov. 15, 1995 Jun. 27 1996 Contents of Modification Initial issue Dletion of HM628127HB-25 series Change of format Change of Block Diagram Function Table Addition of Mode parameter Recommended DC Operating Conditions Change of note 2. Addition of note 3. AC Characteristics Change order of notes Change of Timing Waveform Addition of Read timing waveform(2), (3) Low VCC Data Retention Charactristics Change of Test conditions for I CCDR Change of Package Dimensions Drawn by Y. Saitou Y. Saitou Y. Saitou Approved by K. Yoshizaki K. Yoshizaki A. Ide 3.0 Nov. 19, 1996 14 |
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